A unified approach to the synthesis of fully testable sequential machines

Irredundant sequential machines via optimal logic synthesis

optimal sequential logic synthesis can produce fallv testable nonscan finite state machines. Test generation algorithms can be used It is well known that optimal logic synthesis can ensure fully to remove all the redundancies in sequential machines resulting in testable combinational logic designs. In this paper. we show that fuily testable designs. However. in general. this method requires opt...

Easily testable PLA-based finite state machines

the area and timing penalty associated with LSSD techniques are not acceptable to designers. In this paper, we outline a synthesis procedure, which Logic synthesis and minimization techniques can, in beginning from a State Transition Graph description principle, ensure fully and easily testable combinational of a sequential machine, produces an optimized easily and sequential circuit designs. I...

An Approach for Designing On-Line Testable State Machines

1. Introduction Synthesis of state machines have attracted the attention of researchers for more than two decades. Several state assignment techniques that result in efficient implementation of the next state logic have been developed [1-3]. However, none of these addresses the testability of an implemented machine. A popular approach for enhancing the testability of a state machine is to modif...

Boolean minimization and algebraic factorization procedures for fully testable sequential machines

Synthesis of Fast On-Line Testable Controllers for Data-Domi- nated Applications

A target structure for implementing fast on-line testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatib...